1. Field of the Invention
The present invention relates to a vertical type MOS transistor with stable performance characteristics.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a conventional vertical type MOS transistor. (Taken from "Field-Effect and Bipolar Power Transistor Physics," published by Academic Press in 1981, pp. 280-282.)
The vertical type MOS transistor shown in the figure includes a transistor body region which consists of an N.sup.+ type (high concentration N type) substrate 1 having a drain electrode connected on its bottom surface, and an N.sup.- type (low concentration N type) layer 2 epitaxially grown on the top surface of the substrate 1, and a plurality of P type well regions 3 formed with a.prescribed interval on the top surface of the N.sup.- type layer (referred to as the N.sup.- type drain region hereinafter) 2. Within a P type well region 3, there are provided N.sup.+ type source regions 4, and an oxidized gate region 5 and a gate electrode 6 that bestride over both of an N+ source region 4 and the N.sup.- type drain region 2 which is to function as the effective drain region.
The top surface of a gate electrode 6 is covered by a PSG layer 7, and a source electrode 8 is formed so as to cover the top surface of the PSG layer 7 and to make direct contact with the N.sup.+ type source region 4 and a P.sup.+ type contact region 9 that is formed within the P type well region 3.
The breakdown voltage between the source and the drain of this kind of vertical type MOS transistor is determined by the breakdown voltage of the joined section of the N.sup.- type drain region 2 and P type well region 3. In other words, the higher the impurity concentration of the N.sup.- type drain region 2, the lower is the breakdown voltage between the source and the drain, which results in a decrease in the on-state resistance.
Moreover, since the threshold voltage Vt is determined by the maximum concentration Po at the surface of the P type well region 3, when it is arranged to have both of the breakdown voltage and the threshold voltage to be relatively low, the difference between the impurity concentrations of the N.sup.- type drain region 2 and the P type well region 3 becomes small.
Under these circumstances, when the threshold voltage Vt or the on-state resistance, of a conventional MOS transistor with the above construction, is desired to be low, the depletion layer Dp which develops upon impression of a voltage between the source and the drain spreads with approximately equal widths on the side of the N.sup.- type drain region 2 as well as on the side of the P type well region 3, as shown by the broken lines in FIG. 1. Therefore, when the width of the depletion layer Dp increases, the effective length Le of the channel is diminished (the so-called short channel effect), resulting in changes in the performance characteristics or giving rise to a possibility of causing punch-through due to reach of the depletion layer Dp to the N.sup.+ tye source region 4.